(1) Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory), and more particularly, to a semiconductor memory device which comprises a plurality of banks, as represented by SDRAM (Synchronous DRAM).
(2) Description of the Related Art
DRAM is comprised of a plurality of memory cells, each made up of a capacitor and a transistor, arranged in a matrix form, where a charge is accumulated on the capacitor of each cell to store information. In this DRAM, since the charge accumulated on the capacitor decreases over time, a refresh (re-write) is performed every fixed time for holding the stored information.
SDRAM, in which a memory chip is divided into a plurality of banks and in which memory cells can be independently driven in each bank, is known as one kind of DRAM's. In this SDRAM, a memory cell operation is executed on a bank-by-bank basis in accordance with a command supplied from an external controller (see JP-A-2000-215665).
Several commands are used in the SDRAM, one of which is an auto refresh command. As the auto refresh command is executed in the SDRAM, each bank is sequentially refreshed. Before executing the auto refresh command, each bank is precharged by an all bank precharge command or the like.
The refresh of each bank by the auto refresh command is generally executed in a predetermined order without regard to the order in which each bank was precharged before the execution of the auto refresh command. FIG. 1 illustrates a conventional refresh control circuit used in SDRAM which has four banks A, B, C, D.
The refresh control circuit illustrated in FIG. 1 has delay circuits 100-102 which are connected in series, and the refresh control circuit receives the timing signal “REF” indicative of the timing at which the auto refresh command is executed. The refresh control circuit sequentially generates refresh bank selection signals “REFA,” “REFB,” “REFC,” “REFD” at a timing at which the timing signal “REF” becomes active. The sequence of the transmission of the refresh bank selection signals is fixed. Thus, irrespective of which of banks A-D is precharged last, the refresh operation is performed in the order of banks A, B, C, D. Therefore, if bank A is precharged last (by way of signal “PREA”), followed by the execution of the auto refresh command, bank A is refreshed immediately after bank A was precharged, as illustrated in FIG. 2 (whereby bank A is selected by active command signal A, denoted by “ACTA” in FIG. 2). In this event, the internal tRP (RAS Precharge Time) of bank A becomes shorter, as compared with the other banks, causing difficulties in providing stable information storage operations.